1. Field of the Invention
The present invention relates general to Delay Locked Loops, and more particularly to ways to ensure that a Delay Locked Loop locks to the proper operating state.
2. Background of the Invention
As is well known, Delay Locked Loops (DLLs) are commonly used to generate clock signals that have periods that are sub-multiples of the period of a reference clock signal. A conventional DLL circuit 200, as illustrated, for example, in FIG. 2, comprises a Voltage Controlled Delay Line (VCDL) 202 configured to receive an input clock signal, or reference signal (clk_in). VCDL 202 comprises a plurality of delay blocks 208 configured to delay the input clock signal by a certain amount (TΔ). The delay applied by delay blocks 208 and 210 is controlled via a voltage supply by charge pump 206. It will be understood that VCDL 202 can comprise any number of delay blocks, and that delay blocks 208 and 210 are shown by way of example only.
VCDL 210 produces a clock signal (clk_delay) that is a delayed version of the input clock signal. When DLL 200 is first powered on, the entire circuit must align with, and lock on to, the input clock signal. In order to ensure that this occurs, the delayed clock signal at the output of VCDL 202 is fed to a Phase-Frequency Detector (PFD) 204. In addition, the input clock signal is fed to another input of PFD 204. PFD 204 can be configured to compare the phase of the delayed clock signal with that of the input clock signal and determine whether the delays applied by blocks 208 and 210 should be increased or decreased in order to align the phase of the delayed clock signal with that of the input clock signal.
PFD 204 controls the delays of blocks 208 and 210 by controlling the voltage output by charge pump 206. PFD 204 does this via an up output and a down output that control the voltage produced by charge pump 206. If the delayed clock signal is too slow, then PFD 204 can send up commands to charge pump 206, which will cause charge pump 206 to increase the voltage supplied to delay blocks 208 and 210. Increasing the voltage supplied to delay blocks 208 and 210 will cause the delay (TΔ) to decrease, which should bring the delayed clock signal back into phase with the input clock signal.
Conversely, if the delayed clock signal is too fast, then PFD 204 can send down commands to charge pump 206 which will cause the voltage supply to delay caps 208 and 210 to decrease. Decreasing the voltage supply to delay caps 208 and 210 should increase the delay (TΔ) applied to the input clock signal and should bring the delayed clock signal back into phase with the input clock signal.
FIG. 1 is a timing diagram illustrating waveforms for the various clock signals in DLL 200. As can be seen, the input clock signal (clk_in) has a period (T). The output clock signal (clk_out) can for example be configured to have half the period (T/2), i.e., be twice as fast, as the input clock signal. In the example illustrated in FIG. 1, the delayed clock signal (clk_delay) is delayed by one clock period (T).
When DLL 200 is first powered up, it is possible that it will correctly lock onto the input clock signal; however, there are other possible stable operating points that would produce incorrect results. For example, DLL 200 has no way to know if the delayed clock signal is delayed by exactly one period (T) or if in fact it is delayed by two periods (2 T) or more. When the delayed clock signal is delayed by a multiple of more than one times the input clock period (T), this can be referred to as a too_slow operating condition. In addition, the delayed clock signal can actually be trying to lock to a zero delay state, which is an impossible state. When this occurs, DLL 200 can be set to be operating in a too_fast operating condition.
When DLL 200 is operating in a too_fast or too_slow condition, it can be said to be in a false-lock state. Thus, conventional DLL circuits can suffer from an inability to detect too_fast and too_slow operating conditions, i.e., they suffer from an inability to prevent false-lock conditions.